Power-on Reset

From Appendix B1 of Paul Pham’s master’s thesis.

B.1 Power-On Reset Circuit
The underlying analog layer of an FPGA is usually reset with an RC delay circuit
connected to the positive power supply. However, a similar feature is usually not
available for the digital logic programmed into the FPGA. Many modules use state
machines and variables which must begin in a well-defined state in order to function
properly. The catch is that any power-on reset circuit must not itself depend on any
initialization; all it can use are power, ground, a clock, and combinational gates. The
circuit used in the pulse sequencer’s firmware is shown in Figure B-1.

It is constructed from T flip-flops and produces a pulse one clock cycle wide,
on the first clock cycle after it powers up. Note that this is a structural, or RTL
(register-transfer logic), description using the industry standard Library of Param-
eterized Modules (LPM); in general, RTL descriptions are not otherwise portable.

This circuit depends on the flip-flops powering up in an off state. Many FPGAs,
the Altera Cyclone included, allow one to specify the power-on states of uninitial-
ized registers; thus, the above circuit could be implemented in an equivalent VHDL
behavioral description.