Clock Programming

Posted by Jeff Booth

Overview

One of the components of the pulse sequencer is a clock source.  The source must generate an 800 MHz clock signal for a sine wave generator, and a 100 MHz signal for the processing unit.  Originally, this clock source was provided by an external signal generator, which was both expensive and bulky.  As an alternative, Paul bought a clock source evaluation board, which can be programmed via a serial interface to generate a 1600 MHz clock signal.  Unfortunately, this board must be programmed every time it is powered on, requiring a computer and a serial cable.  Jeff’s project is to program the clock from the processing unit when the system powers on, and then convert the 1600 MHz signal to 800 MHz and 100 MHz signals.

The Clock Source

For the clock source, Paul bought an ADF-4360-2 chip on an EB1 Rev. D3 evaluation board.  This board has a connector for a 9V battery; since the battery died, we connected it to a 12V power source (since the on-board voltage regulator can handle it).  It has a clock output labeled “RF” and a DB9 female connector for communications.  The pin mappings are:

3. CLK – Clock
5. Data
7. LE – Latch Enable
8. GND – Ground

Every time CLK transitions from low to high, the bit on Data is read into the least-significant bit of a shift register.  Once 20 data bits are read, followed by 2 address bits, LE should be raised high.  This will cause the data in the shift register to be transferred to the register indicated by the address bits.  There are three registers that must be programmed in this order: R, Control, then N.  Here are the 22-bit values to shift in for each register, which Jeff found by clicking the “Registers” button in the clock source’s control program on an attached desktop computer:

R: 0000 0000 0000 0000 1100 1001
Control: 1000 1111 1111 0001 0000 1100
N: 0000 0000 1111 1010 0000 0010

Clock Divider

The AD9513 clock divider is programmed by 11 pins, each having one of 4 different voltage levels.  Our desired configuration produces CMOS voltage levels on two ports.  Port OUT0, on the connector labeled J1, divides the clock input frequency by 16.  Port OUT1, on connector J3, divides the clock input frequency by 2

Jumper configuration on the clock divider board

DB-9 female connector from the computer; plugs into the clock source.

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